// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2023-2024, Phytium Technology Co., Ltd.
 * lixinde             <lixinde@phytium.com.cn>
 * weichangzheng       <weichangzheng@phytium.com.cn>
 * Phytium pe2201 Soc information header.
 */

#ifndef _FT_PE2201_H
#define _FT_PE2201_H

/* QSPI */
#define QSPI_BASE                       0x28008000
#define QSPI_FLASH_CAPACITY_REG         (QSPI_BASE + 0x0)
#define QSPI_ADDR_READ_CFG_REG          (QSPI_BASE + 0x4)
#define QSPI_CMD_PORT_REG               (QSPI_BASE + 0x10)
#define QSPI_LD_PORT_REG                (QSPI_BASE + 0x1C)

/* QSPI FLASH */
#define FLASH_BASE                      0x38040000

/* PWM */
#ifdef PE2201_BMC_SYS
#define PWM_BASE                        0x2804c000
#else
#define PWM_BASE                        0x2804d000
#endif

#define PWM_TIM_CTRL_REG                (PWM_BASE + 0x404)
#define PWM_PERIOD_REG                  (PWM_BASE + 0x40c)
#define PWM_CTRL_REG                    (PWM_BASE + 0x410)
#define PWM_CCR_REG                     (PWM_BASE + 0x414)

/* LSD */
#define LSD_PWM_REG                     0x2807e020
#define LSD_NAND_MMCSD_HDDR             0x2807e0c0

/* onewire */
#define ONEWIRE_BASE                    0x2803f000

/* USB */
//USB2.0
#define USB2_0_BASE                     0x32800000
#define USB2_1_BASE                     0x32840000
#define USB2_0_UIB                      0x32880000
#define USB2_0_PHY                      (USB2_0_UIB + 0x1000)
#define USB2_1_UIB                      0x328c0000
#define USB2_1_PHY                      (USB2_1_UIB + 0x1000)
#define SECSID_ATST_USB2_REG            0x0004
#define USB2_PHY_REFCLK_MODE            0x002c
#define OVERCURRENTN_CTRL_REG           0x0038
#define HCUSBIRQ_REG                    0x018d

//VIRTUAL HUB
#define VHUB_USB2_0_PHY                 0x31980000
#define DEV1_CFG                        0x31990000
#define DEV2_CFG                        0x319a0000
#define DEV3_CFG                        0x319b0000
#define VHUB_CFG                        0x319c0000
#define UTMIP_CFG                       0x0020
#define CONFIG_VHUB_USB2_0_PHY          0x1004

/* KCS */
#define KCS_ENABLE_REG                  0x28010200

/* DP */
#define DP_DST_ADDR                     0x32b3a008

/* UART */
#define UART0_BASE                      0x2800c000
#define UART1_BASE                      0x2800d000
#define UART2_BASE                      0x2800e000
#define UART3_BASE                      0x2800f000

/* I2C/PMBUS/SMBUS */
#define PMBUS0_BASE                     0x28011000
#define PMBUS1_BASE                     0x28012000
#define SMBUS_BASE                      0x28013000

/* MIO */
#define MIO00                           0x28014000
#define MIO01                           0x28016000
#define MIO02                           0x28018000
#define MIO03                           0x2801a000
#define MIO04                           0x2801c000
#define MIO05                           0x2801e000
#define MIO06                           0x28020000
#define MIO07                           0x28022000
#define MIO08                           0x28024000
#define MIO09                           0x28026000
#define MIO10                           0x28028000
#define MIO11                           0x2802a000
#define MIO12                           0x2802c000
#define MIO13                           0x2802e000
#define MIO14                           0x28030000
#define MIO15                           0x28032000

#define MIO_CTRL_OFFSET                 0x1000
#define MIO_FUNC_SEL                    0x00
#define MIO_FUNC_SEL_STATE              0x04
#define MIO_VERSION                     0x100

#define MIO_I2C                         0x00
#define MIO_UART                        0x01

/* GPIO */
#define GPIO0_BASE                      0x28034000
#define GPIO1_BASE                      0x28035000
#define GPIO2_BASE                      0x28036000
#define GPIO3_BASE                      0x28037000
#define GPIO4_BASE                      0x28038000
#define GPIO5_BASE                      0x28039000
#define GPIO_SWPORTA_DR                 0x00
#define GPIO_SWPORTA_DDR                0x04
#define GPIO_EXT_PORTA                  0x08

/* Platform SATA */
#define PSU_SATA_BASE                   0x31a40000
#define GSD_SATA_BASE                   0x32014000
#define SATA_CAP                        0x0
#define SATA_PI                         0xC
#define SATA_P_CMD                      0x118

/* WDT */
#define WDT0_BASE                       0x28040000
#define WDT_WCS                         0x1000

/* SCMI */
//Mailbox address space
#define MBX_BASE                        (0x32a00000)
#define MBX_SCP_UBOOT_BASE              (MBX_BASE + 0x20)
#define MBX_UBOOT_SCP_BASE              (MBX_BASE + 0x120)
#define MBX_CONFIG_BASE                 (MBX_BASE + 0x500)
#define AP_UBOOT_CONFIG                 (MBX_CONFIG_BASE + 0xc)
#define AP_UBOOT_SET                    (MBX_UBOOT_SCP_BASE + 0x8)

//MBX OS chanle address
#define MBX_SCP_OS_BASE                 (MBX_BASE + 0x0)
#define MBX_OS_SCP_BASE                 (MBX_BASE + 0x100)
#define SHARE_MEM_BASE                  (0x32a10000)
#define SCP_TO_AP_OS_MEM_BASE           (0x32a10000 + 0x1000)
#define SHARE_MEM_ETH_TRAINING          (SCP_TO_AP_OS_MEM_BASE + 0x864)
#define AP_TO_SCP_OS_MEM_BASE           (0x32a10000 + 0x1400)

//shared memory base
#define AP_TO_SCP_SHARED_MEM_BASE       (0x32a10000 + 0xC00)
#define SCP_TO_AP_SHARED_MEM_BASE       (0x32a10000 + 0x800)

/* PAD */
#define PAD_BASE                        0x32B30000
#define DS_AG55                         0x005c
#define DS_AG53                         0x0060
#define DS_AE55                         0x0064

/* CPU RESET */
#define CPU_RESET_POWER_ON              0x01
#define CPU_RESET_CORE                  0x03
#define CPU_RESET_WATCH_DOG             0x80

/* ETH */
#define GMAC0_BASE_ADDR                 0x3200c000
#define GMAC1_BASE_ADDR                 0x3200e000
#define GMAC2_BASE_ADDR                 0x32010000
#define GMAC3_BASE_ADDR                 0x32012000
//ETH PHY
#define GSD_PHY0_BASE                   0x32100000
#define GSD_PHY1_BASE                   0x32200000
#define GSD_PHY2_BASE                   0x32300000
#define GSD_PHY3_BASE                   0x32400000

/* IACC */
#define IACC_REG_BASE                   0x28052000
#define REG_CACHE_MODE                  0x0008

/* JPEG */
#define JPEG_ENCODER_BASE               0x32b32000
#define JPEG_TRANSFORM_INFORMATION      0x0804
#define JPEG_STATUS_INTERRUPT           0x0808

/* TACHO */
#define TACHO30                         0x28072000
#define TACHO31                         0x28073000
#define TIMER_TACHO_CTL                 0x000
#define TIMER_TACHO_INTR_STS            0x02c

#endif /* _FT_PE2201_H */
